1. Field of the Invention
The present invention generally relates to packaging of semiconductor devices formed on multiple chips and, more particularly, to the manufacture of a modular device with plural semiconductor chips including high power devices and/or high performance, high-density processors, memories, application specific integrated circuits (ASICS) and logic devices.
2. Description of the Prior Art
It has long been recognized that reduction of size of circuit elements and reduction of spacing and length of connections therebetween in integrated circuits and electronic packages containing one or more integrated circuit chips provides both economies of manufacture and performance improvements. Reduced size of circuit elements generally provides reduced parasitic capacitance and inductance and improved switching speed. Closer spacing of circuit elements on chips, especially in combination with reduced circuit element size, provides potentially increased functionality of each chip while allowing processing costs, which are generally fixed on a "per-wafer" basis, to be spread over an increased number of chips. Reduced connection length reduces signal propagation time and susceptibility to noise.
However, as is well-known, power dissipation from transistors is at a maximum during switching (and, ideally, zero when a transistor is fully turned on or off). Increased switching speed is generally exploited to improve performance by reducing switching cycle time so that the switching interval is maintained at about the same percentage of cycle time as cycle time is reduced. Therefore, heat dissipation per element increases with reduction in cycle time and further increases per unit chip area as integration density increases. Higher operating temperatures can only be utilized to a limited degree in increasing heat dissipation since semiconductor devices will degrade in performance or be destroyed if temperature limits are exceeded.
Thus, for high-performance digital switching circuits (and, of course, analog and power circuits, as well) heat dissipation is a limitation on performance and, as a practical matter, on integration density, forcing a trade-off between manufacturing costs and potential performance while limiting improvements in both. For that reason, where high performance is required and of paramount importance, sophisticated cooling systems including circulation of liquids or cooled gases have often been employed. Such cooling systems are, themselves, very expensive in terms of both manufacturing costs and integration with complex and compact electronic systems, limiting miniaturization and imposing at least two additional failure modes.
Specifically, such cooling systems are generally of a geometry and configuration which displaces or prevents the significant utilization of convection or radiant heat transfer and, of course, are subject to malfunction which would allow temperature limits to be exceeded very quickly. Further, the actual heat required to be dissipated depends of the actual number of switching transitions which occur.
Further, while average numbers of switching cycles at a given cycle time may be statistically projected, the number is subject to wide variation, particularly with high-performance so-called dynamic logic circuits which (as distinct from dynamic memories which are periodically refreshed) are precharged to particular logic state prior to each switching cycle and thus switch only as required. Therefore, cooling systems which rely on a large temperature differential between chips and coolant fluid for efficiency may cause wide temperature excursions and thermal cycling of chips which may also degrade the structures therein (e.g. by metal fatigue or migration and internal semiconductor stresses which may be relieved by formation of crystal dislocations that may thereafter trap charge, cause leakage, etc.). Thus, the importance of the nature of packaging of integrated circuits to utilize naturally occurring heat transfer mechanisms such as convection or highly reliable forced air cooling at ambient temperature, where possible, is of great importance to performance, reliability and economy of manufacture of electronic devices which may contain integrated circuit packages.
In this regard, the "footprint" of electronic circuit packages on a substrate to which the circuit package may be attached is also of importance to complete device performance in the same manner as small circuit element size and short connection length provides performance advantages on individual chips and within integrated circuit packages. Similarly, when fine patterns of electrical conductors are formed at close spacing on such a substrate, manufacturing yield generally decreases with increase of substrate area.
To minimize connection length and minimize the area occupied by an integrated circuit package, it is known to stack chips parallel to a substrate on which the package is to be mounted or to mount the chips vertically (e.g. orthogonal to the substrate), making connections along the edges of the chips. However, increased density of package mounting is subject to the same problems of heat dissipation at the level of the substrate area as discussed above in connection with chip area. Further, vertical mounting of chips generally provides less support and structural robustness of the chip mounting structure. Thus savings in area to provide increased proximity of packages can be easily defeated by the requirement for large heat sinks and chip mounting structures which may be required to have a greater area "footprint" on a supporting structure than the integrated circuit chip or package itself.
In this regard, the length of heat conduction through the heat sink, itself, must also be considered in the efficiency of the design thereof together with package mounting density and maximum or even adequate thermal performance is seldom consistent with maximum electrical performance and compactness. Additionally, heat transfer from the edge of a chip is necessarily poor and generally requires conduction of heat through the semiconductor substrate of the chips. Transfer of heat to such a heat sink is also problematical since intimate thermal contact of the chips to the heat sink is usually achieved through the use of a thermally conductive grease which presents two thermal boundaries and is of relatively low thermal conductivity. Use of a thermal paste also presents the problem of confining it to the desired location which may be complicated structurally and, if confinement is not effective, may result in unexpected loss or compromise of the heat transfer function.
Recently, there has been interest in graphite and graphite composite materials, in particular, for conduction of heat, particularly in extremely high temperature environments such as in jet engines and high speed airframes. Some applications to electronics have been suggested, as well, although no admission is made that any such suggestions constitute prior art as to the present invention. These materials have several potential advantages for such applications in that heat conduction, at least in a single plane, can be quite high (e.g. about three times that of copper). Additionally, by appropriate choice of additives and fillers, it is possible to closely match the coefficient of thermal expansion (CTE) of such materials to that of semiconductor substrate materials such as silicon or germanium or any other materials used in packaging so that changes of temperature do not result in significant mechanical stresses in a semiconductor chip to which such materials may be attached.
On the other hand, while copper is thermally conductive isotropically, these graphite and graphite/fiber composite materials generally are anisotropically thermally conductive, exhibiting much lower heat conductivity (e.g. about one-quarter to one-third that of copper or about ten percent or less of the heat conductivity in the preferred heat conduction direction) in other directions. Further, while graphite composite materials are generally much more electrically resistive than copper or other materials commonly used for conductors in electronics packages (e.g. 10x-100x), they are far too conductive to be considered insulators. As is generally known, materials which exhibit good thermal conductivity also exhibit good electrical conductivity and vice-versa. Conversely, electrically insulative materials can generally be expected to exhibit poor thermal conductivity.
Accordingly, while electrically conductive materials may be used for relatively large structures, such as making thermal connections from heat sources to heat sinks of potentially substantial length (e.g. having a total thermal resistance comparable to any insulator placed in the thermal path) as has been known for the so-called "heat-pipe", it is not clear that they are usable in chip-level electronic packaging or that, even if so usable, they would provide any advantage in chip packaging density at either the package or substrate level or support any gain in electrical performance by overall reduction of connection length.
Accordingly, it is seen that there is a need for an overall solution to the concurrent problems of integration density, packaging compactness, structural robustness of packaging, package mounting area and density and heat transfer from chips to a heat sink structure having a high efficiency of heat dissipation through simple heat transfer mechanisms, such as convection.